1. Field of the Invention
The present invention relates to a circuit board used in electrical and electronic devices, a method for manufacturing the same, and a semiconductor device.
2. Description of Related Art
Following the reductions in size and profile and the high functionality of electronic devices in recent years, there has been an increasingly strong demand for the high densification of electronic components mounted on circuit boards and the high functionalization of circuit boards on which electronic components are mounted. Particularly following the high densification and high integration of semiconductor integrated circuits (LSI), rapid advances have been made in increasing the pin count and narrowing the pitch of electrode terminals in LSI chips. Small packages such as ball grid arrays (BGA), land grid arrays (LGA) and chip scale packages (CSP), and the flip-chip mounting of area bumps have been developed as high density mounting techniques that are compatible with this.
A method of flip-chip mounting a semiconductor element that is generally used, for example, involves forming solder bumps on the electrodes of the semiconductor element and solder mounting the bumps to an interposer. As for the method of mounting a small package such as a CSP to a circuit board, a connection method that involves supplying solder paste to a circuit board or the electrode portion of a semiconductor package, mounting the semiconductor package on the circuit board, and connecting the semiconductor package to the circuit board using reflow soldering generally is used.
With a solder connection such as this, the reliability of the connecting portion decreases due to the difference in thermal expansion coefficient between the interposer and the semiconductor element or between the circuit board and the semiconductor package. In particular, a major cause of electrical connection failure is stress that occurs in a connecting portion made up of different materials as a result of temperature differences associated with the environment and the device being turned ON/OFF, which leads to cracking or the like in the solder connecting portion.
Given this situation, a number of methods have been proposed in order to avoid connection failure at the connecting portion. For example, a method disclosed in JP H11-087424A involves improving the consistency of the thermal expansion coefficient, together with reinforcing the connecting portion via sealing resin, by filling the gap between the semiconductor chip and the printed wiring board with sealing resin.
However, when the gap between the semiconductor chip and the printed wiring board is filled with sealing resin, the thermal expansion coefficient in the thickness direction differs between the connecting portion and the sealing resin portion, which means that connection reliability cannot necessarily be improved even if the consistency of the thermal expansion coefficient in a direction (surface direction) orthogonal to the thickness direction can be improved. Also, filling the gap with sealing resin is not preferable due its effect on productivity, since it not only increases the lead time but uses additional material, making it desirable to improve connection reliability without using sealing resin.
Connection structures that do not use sealing resin include flip-chip mounting configurations such as that disclosed in JP H10-209203A have been proposed. The configuration disclosed in JP H10-209203A has an insulating layer provided on part of a supporting substrate, a wiring layer formed so as to extend across the surfaces of both the insulating layer and the supporting substrate and a semiconductor element bump-bonded to the wiring layer, and is characterized by the adhesive strength of the bump-bonded portion being greater than the adhesive strength of any other interface.
However, the above semiconductor device cannot adopt electrode structures such as a pad-on-via structure and is not compatible with narrow pitch mounting, since the wiring needs to be routed in a different location to the bump-bonded portion. Since the adhesive strength between the semiconductor element and the substrate is dependent on a weakly bonded portion, the overall bonding strength is reduced in comparison to conventional solder mounting, making it difficult to maintain the level of drop impact reliability required by mobile devices and the like.
The present invention was made to solve the above problems, and provides a circuit board that has high connection reliability and enables narrow pitch mounting, a method for manufacturing the same, and a semiconductor device.